Does The Country Need A Good $20 Microprocessor?

Robert Sugarman
Electronic Engineering Times

August 25, 2975

Norristown, PA - Is MOS Technology offering a high-performance microprocessor at single unit prices of $20 just to buy into the CPU business? And, if so, will low profits keep them from providing software and other crucial customer support?

Any answer to these questions based on single-piece prices is probably irrelevant. For one thing, documentation sent out with single-piece orders probably costs more than the CPU itself. For another, only high-volume competition will determine whether the CPU gains a foothold in the marketplace. The company's product manager, Chuck Peddle, claims that, by virtue of high yield on a carefully planned minimum chip size, he'll compete successfully with enough profit left for reinvestment in ample user support. It isn't going to be easy, though, in view of the recent erosion in volume processor prices. Peddle admits other vendors have already come close to him in high-volume pricing.

"I've deliberately set the single-piece price low enough," says Peddle, "so that anyone looking for TTL replacement in control and measurement systems can't overlook it. We've spoken to over 100 accounts and many of them just won't use, for example, a $40 CPU to interconnect a bunch of PTAs (peripheral interface adapters) they can buy for about $6 each in volume."

As for software, "It pays for itself," says Peddle, "at least at the prices set by my competition. Anyway, as part of the price for getting into the business, we are committed to full software support, as well as to a real-time multiprocessor simulating and debugging system .

"The small CPU chip size," Peddle continues, "was a planned effort from the beginning of our design effort.

"We decided on a memory-oriented CPU like the Motorola 6800 rather than one with general-purpose internal registers like the Intel 8080. Internal registers are fine until you run out of registers for a given problem, in which case a lot of extra address coding is required.

"Since the limiting factor in designing to a given chip size is having enough metallization for the instruction data-transfer paths, we talked to potential customers about what instructions they really needed and what could be omitted.

"As a result," Peddle explains, "we left out double-byte stores and reduced the number of machine states from Motorola's 13 to just seven. Then we used a very large ROM rather than hardwired logic for control, which, contrary to industry opinion that ROM take too much space, actually reduce the chip size."

While Peddle admits that going to seven states means he can't dump any recall all the CPU contents as quickly as the Motorola 6800 during an interrupt, he claims it's worth it in reduced chip area. "We tried an eight-state machine which would dump the accumulator as well as the progran counter and status," he says, "but since it added another 10 mils to the chip, we discarded it."

As for benchmark contests on byte count, Peddle says he's won several of them over equivalent CPUs by 20 percent, but doesn't claim he'll win them all. "I'll lose to a user," he admits "with a benchmark that makes optimum use of all the internal registers of the 8080."

He does claim a general speed advantage per instruction over competitors, though, with typical clock rates of 2 MHz. "One reason for the high clock rate," Peddle says, "is that the large ROM reduced our logical interconnect levels to five and cue overall propagation times."

Copyright 1975