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From: dfh@scirtp.UUCP
Newsgroups: net.arch
Subject: help choosing cache sizes
Message-ID: <565@scirtp.UUCP>
Date: Sat, 22-Feb-86 12:20:23 EST
Article-I.D.: scirtp.565
Posted: Sat Feb 22 12:20:23 1986
Date-Received: Wed, 26-Feb-86 03:28:57 EST
Distribution: net
Organization: SCI Systems, Research Triangle Park, NC
Lines: 19

Our hardware folks are starting to design a CPU board using the 80386 and
they asked me what size and type of on-board cache would be optimum for a 
UNIX environment.  I have no idea.

The box is (will be) an 80386 with 80186 I/O processors using multibus
I.  There is a high speed memory bus from the CPU to the expansion
memory card(s).  The current implementation uses an 10 MHz 80286 at 0
wait states in lieu of the '386.

Has anybody else looked at the '386 with this in mind yet?

What cache sizes are common in other microprocessor systems?

Pointers to literature on the subject appreciated.

				David Hinnant
				SCI Systems, Inc.
				...{decvax, akgua}!mcnc!rti-sel!scirtp!dfh

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